1. Field of the Invention
The present invention relates generally to signal translating circuits and more particularly is directed to a signal translating circuit suitable for use in a scanning or driving circuit for driving a CCD (charge-coupled device) image sensor or imager, a liquid crystal display device, a memory device and so on.
2. Description of the Prior Art
FIG. 1 shows a prior art circuit which has been used as such signal translating circuit.
In FIG. 1, an input terminal 1 is connected to the gate of a MOS (metal oxide semiconductor) transistor T.sub.1 of enhancement type. The source of the transistor T.sub.1 is connected to a ground line 2 and the drain thereof is connected to the source and the gate of a MOS transistor T.sub.2 of depletion type. The drain of the transistor T.sub.2 is connected to a power source line 3.
The connection point between the drain of the transistor T.sub.1 and the source of the transistor T.sub.2 is connected through the source-drain path of a MOS transistor T.sub.31 of enhancement type which forms a transmission gate to transistors T.sub.41 and T.sub.51 which are connected to each other in the same way as in the transistors T.sub.1 and T.sub.2. The connection point between the transistors T.sub.41 and T.sub.51 is connected through the source-drain path of a MOS transistor T.sub.61 of enhancement type which forms a transmission gate to transistors T.sub.71 and T.sub.81 which are connected in the same way as in the transistors T.sub.1 and T.sub.2.
The circuit formed of the transistors T.sub.31 to T.sub.81 is repeatedly connected in turn. In the figure, the upper numeral of reference letter T is used common and the lower number thereof is changed in turn.
Clock terminals 4 and 5 to which clock signal .phi..sub.1 and .phi..sub.2 different in phase are applied are respectively connected to gates of the transistors T.sub.31, T.sub.32 . . . and T.sub.61, T.sub.62 . . . .
In this circuit, the clock signals .phi..sub.1 and .phi..sub.2 as shown in FIGS. 2A and 2B are respectively supplied to the clock terminals 4 and 5, while a signal .phi..sub.IN as, for example, shown in FIG. 2C is supplied to the input terminal 1.
Thus, an inverted voltage V.sub.1 as shown in FIG. 2D appears at the connection point .circle.1 between the transistors T.sub.1 and T.sub.2.
The inverted signal V.sub.1 is then sampled by the clock signal .phi..sub.1 and held in the gate .circle.2 the transistor T.sub.41 so that a voltage V.sub.2 as shown in FIG. 2E appears thereat. Thus, an inverted voltage V.sub.3 as shown in FIG. 2F appears at the connection point .circle.3 between the transistors T.sub.41 and T.sub.51. This inverted voltage V.sub.3 drives, for example, the first horizontal scanning line.
Further, the inverted voltage V.sub.3 is sampled by the clock signal .phi..sub.2 and then held in the gate the transistor T.sub.71, resulting in a voltage V.sub.4 as shown in FIG. 2G thereat. Thus, voltages V.sub.5, V.sub.6 and V.sub.7 as shown in FIGS. 2H, 2I and 2J appear respectively at the connection point .circle.5 between the transistors T.sub.71 and T.sub.81, the gate .circle.5 of the transistor T.sub.42 and the connection point .circle.7 between the transistors T.sub.42 and T.sub.52. The voltage V.sub.7 thus generated drives the second horizontal scanning line. The above operation is sequentially performed hereinbelow.
Assume that the threshold value of the transistors T.sub.31, T.sub.61 . . . each forming the transmission gate is V.sub.th. Then, if the condition of V (.phi..sub.1, .phi..sub.2) p-p.gtoreq.V.sub.DD +V.sub.th (where V.sub.DD represents the voltage of the power source line 3) is satisfied, a signal is transmitted through the transmission gate.
In this way, the input signal .phi..sub.IN is sequentially transmitted to drive each horizontal scanning line in turn.
The above circuit, however, requires six transistors for constructing one stage by which the signal is transmitted and the succeeding signal is produced. For this reason, the circuit becomes large in size, and particularly when the circuit is formed as an IC (integrated circuit), the chip area is increased, resulting in a problem such as the increased manufacturing cost of IC and so on. More specifically, since in the above circuit the signals are respectively inverted by the transistors T.sub.41, T.sub.51 and T.sub.71, T.sub.81, the transistors of the doubled number are necessary for providing the signal of the same phase.
Also in the above circuit, when a capacitive load is connected to the output side thereof, the waveforms of the output signals V.sub.3 and V.sub.7 shown in FIGS. 2F and 2J are blunted as shown by broken lines. In this case, an overlap is caused between the adjacent output signals. Thus, when the above circuit is employed, for example, for the image sensor, its resolution is deteriorated and the picture quality is deteriorated by the mixed color.
Further, since in the above circuit, the transistors T.sub.2, T.sub.51, T.sub.81 . . . are in the state of being turned on at all times, a through type current flows under the state that the transistors T.sub.1, T.sub.41, T.sub.71 . . . are turned on, consuming a quite large power.
Moreover, since each transistor is driven in the saturation region, a large power is consumed particularly when the circuit is driven at high speed.
Furthermore, since the transistor elements different in type as enhancement type and depletion type are employed, many manufacturing processes are required when the signal translating circuit is formed as, for example, the integrated circuit.
In addition, in the above circuit, the low levels of the waveforms at the output points .circle.3 , .circle.7 . . . are determined by the ratio of on-resistances between the transistors T.sub.41, T.sub.51 and T.sub.42, T.sub.52 . . . so that there occurs a residual voltage V' determined as ##EQU1## where r.sub.1 represents the on-resistance value of the transistors T.sub.41, T.sub.42 . . . , r.sub.2 that of the transistors T.sub.51, T.sub.52 . . . , and V.sub.SS the voltage at the ground line 2. In this case, to reduce the residual voltage V', it is sufficient to increase the ratio between the on-resistance values r.sub.1 and r.sub.2. This means that the chip area of the transistors T.sub.41, T.sub.42 . . . must be made larger than that of the transistor T.sub.51, T.sub.52 . . . , which fact is not desirable. On the other hand, when the MOS transistor is driven by the output signal, if there is the residual voltage V' as described above, many restrictions are brought about by the threshold value and so on. Furthermore, there is a defect that the dynamic range of the signal is reduced by the amount of the residual voltage V', etc.